Xilinx vs Altera vs Lattice 2026: Complete FPGA Comparison

AMD Xilinx, Altera, and Lattice Semiconductor all sell programmable logic. They do not sell interchangeable catalogs. A 100G networking line card, a board-management controller, and a battery-powered camera bridge can all use an “FPGA” and still have almost no overlap in density, power, I/O, package, software, or sourcing risk.

Xilinx products are part of AMD. Altera has operated as an independent FPGA company again since 2025, after Silver Lake took a 51% stake and Intel retained 49%. Lattice remains independent and now sells mid-range Avant devices on top of its small, low-power families.

• Board control, instant-on glue logic, MIPI/video bridging, or a tight power/package budget — start with Lattice, then check whether a small AMD Spartan/Artix or Altera MAX/Agilex 3 part is enough.
• DSP, high-speed serial, mature IP, or a path into a larger AMD platform — start with AMD Xilinx.
• Agilex roadmap, mid-to-high bandwidth, HBM/CXL/RF options, or an existing Quartus design — start with Altera.

This page compares current families, resources, power and I/O, tools, applications, cost, availability, and lifecycle. It is written for design and purchasing teams who still have to put a real ordering code on a BOM. For stocked Xilinx and Altera parts, use the manufacturer pages or send the BOM.

Xilinx vs Altera vs Lattice at a Glance

Use this table to decide which catalog to open first. It is not a device scorecard. Two parts from the same vendor can differ more than two parts from different vendors.

Comparison	AMD Xilinx	Altera	Lattice Semiconductor
Company status in 2026	Xilinx technology and products are part of AMD	Independent FPGA company; Silver Lake 51%, Intel 49%	Independent public semiconductor company
Current key platforms	7 Series, UltraScale, UltraScale+	Agilex 3/5/7/9	Nexus, Nexus 2, Avant
Well-known FPGA families	Spartan, Artix, Kintex, Virtex	MAX, Cyclone, Arria, Stratix, Agilex	iCE40, MachXO, ECP5, Certus, CrossLink, Avant
Representative current products	Spartan 7 and UltraScale+, Artix 7 and UltraScale+, Kintex UltraScale+, Virtex UltraScale+	MAX 10, Cyclone 10, Agilex 3/5/7/9	iCE40, MachXO4/5-NX, Certus-NX, CrossLink-NX, Avant
Main design environment	Vivado; Vitis for software and acceleration	Quartus Prime (Pro for newer Agilex)	Radiant, Diamond, Propel
Portfolio emphasis	Cost-optimized FPGA through high-density programmable computing	Compact devices through high-bandwidth, memory- and RF-intensive FPGA	Small/low-power control and bridging, plus newer mid-range
Common first-look designs	Industrial, networking, communications, vision, aerospace and defense, compute	Industrial, communications, data center, embedded, RF and compute	Board control, interface bridging, embedded vision, edge, industrial
BOM line still needs	Family + device + package + speed + temperature + revision	Same; watch Intel-era vs Altera-era ordering codes	Same; confirm Radiant vs Diamond family support
Typical sourcing path	Xilinx FPGA/CPLD cover and shortage support	Altera/legacy Intel FPGA cover and shortage support	Cross-reference when the design can accept another family

AMD also sells Zynq and Versal adaptive SoCs. Those are not drop-in FPGA line items. Altera’s current roadmap is centered on Agilex, while MAX 10, Cyclone 10 and Arria 10 still appear on long-lifecycle boards. Lattice is no longer only a small-FPGA vendor; Avant is the reason older “Lattice = tiny LUT” comparisons are incomplete.

Xilinx and Altera listings are on the manufacturer pages when those devices are already on the approved vendor list. Lattice belongs in the comparison when power, package, or bridging is the constraint—not because a headline ranked it first.

Company Background in 2026

The three names in this comparison no longer map to the companies that engineers learned a decade ago. Xilinx is a product lineage inside AMD. Altera is again a standalone FPGA company after years as an Intel division. Lattice never left independence, but it is no longer only a small-FPGA specialist. The silicon on a board may still carry an older brand; the current catalog and roadmap use the names below.

AMD Xilinx

Xilinx was one of the companies that turned FPGAs into a commercial market. AMD completed its acquisition of Xilinx on 14 February 2022. The FPGA, adaptive SoC, and related programmable-computing products now sit inside AMD.

The Xilinx name has not disappeared from devices, datasheets, development boards, or existing designs. In a 2026 comparison, it is clearer to say AMD Xilinx when referring to the current portfolio, and Xilinx when referring to long-running family names such as Spartan, Artix, Kintex and Virtex.

AMD also splits that portfolio in a way older “Xilinx FPGA” shorthand ignores:

• Conventional FPGA families: Spartan, Artix, Kintex and Virtex, including 7 Series, UltraScale and UltraScale+
• Adaptive SoCs that combine programmable logic with Arm processors: Zynq
• Adaptive SoC/ACAP platforms: Versal

Those three groups share a vendor and a toolchain. They do not share the same density, I/O, power or software model. This article compares the FPGA families against Altera and Lattice. Zynq and Versal belong in a separate shortlist when the design actually needs that class of device.

Altera

Intel acquired Altera in 2015 and ran the FPGA business as an Intel product line. The Altera brand later returned as the business moved toward operational independence. That change became concrete in September 2025, when Silver Lake completed the acquisition of a 51% stake and Intel retained 49%. Altera now operates as an independent pure-play FPGA company rather than as a wholly owned Intel FPGA division.

Two catalogs therefore coexist in the field. Older boards, markings and PDFs may still say Intel FPGA. Current Agilex pages, software and corporate material use Altera. The device is the same generation of product; the brand on the document is not a reliable way to date it.

The product story is a transition rather than a clean replacement. Agilex 3, 5, 7 and 9 are the current architecture ladder, from compact parts through high-bandwidth, memory-rich and RF-oriented devices. MAX, Cyclone, Arria and Stratix families remain the installed base on a large number of industrial, communications and embedded systems. A 2026 comparison has to keep both layers in view: the roadmap and the boards that are still shipping.

Lattice Semiconductor

Lattice took neither of those paths. It remains an independent public semiconductor company and has kept its center of gravity in low-power programmable logic for communications, computing, industrial, automotive and consumer designs.

For years that meant small FPGAs used for control, interface bridging, connectivity and power-conscious boards: iCE40, MachXO, ECP5, CrossLink and the Nexus-class Certus devices. That description is still accurate for much of the volume. It is no longer complete.

The Avant platform is Lattice’s move into mid-range FPGA territory. Avant-G, for example, reaches up to 637K system logic cells and adds SerDes, external-memory support and resources meant for heavier processing than Lattice’s traditional parts. A comparison that still treats Lattice as “the tiny FPGA vendor” will miss the devices that now overlap the lower mid-range of AMD and Altera.

Lattice does not, and does not claim to, cover the largest AMD and Altera densities. Its position in 2026 is narrower at the top and stronger at the small-power, small-package and bridging end of the market.

FPGA Product Families

Family names are more useful than vendor names. Comparing an iCE40 with a Virtex UltraScale+ is not a vendor comparison. The two parts do different jobs.

AMD Xilinx FPGA Families

Family	Position	Typical design areas	What usually appears on an RFQ
Spartan	Cost- and I/O-oriented FPGA	Control, industrial I/O, board management	Spartan-7/Spartan UltraScale+ plus package and speed
Artix	Cost- and power-conscious, more DSP and serial I/O	Embedded vision, communications, industrial processing	Artix-7/Artix UltraScale+; call out transceiver count if used
Kintex	Mid-range FPGA	DSP, networking, video, data acquisition	Kintex-7/Kintex UltraScale+; package and speed dominate price
Virtex	High-density/high-performance FPGA	High-bandwidth networking, advanced DSP, compute	Virtex UltraScale+; expect long-lead and allocation behavior

7 Series devices (Spartan-7, Artix-7, Kintex-7, Virtex-7) are still widely designed-in. UltraScale and UltraScale+ are the newer architectural layers. Artix UltraScale+ already reaches 1,200 DSP slices and 16.375 Gb/s transceivers inside a “cost-optimized” label—so the family name alone does not fix the capability or the price.

Do not put Zynq or Versal on the same RFQ line as these FPGA families unless the schematic actually uses those devices.

Altera FPGA Families

Altera is mid-transition: long-running families on one side, Agilex on the other.

Family	Position	2026 design status	RFQ note
MAX 10	Small, non-volatile FPGA	Still common for control and instant-on	Often easier to source than a new Agilex 3 if the board already uses it
Cyclone 10	Cost-optimized FPGA	Established low- to mid-range	Confirm LP vs GX; they are not one price class
Arria 10	Mid-range FPGA	Mature, still relevant	High chance of last-time-buy conversations on some OPNs
Stratix 10	Higher-performance FPGA	Established high-end	Treat as a dedicated high-end search, not a Cyclone alternative
Agilex 3	Compact/cost-oriented	Newer entry; transceivers up to 12.5 Gb/s	Use for new compact designs that want the current roadmap
Agilex 5	Mid-range	E-Series ~50K–656K LEs; D-Series beyond 1.6M LEs	State E- vs D-Series; tensor blocks and transceivers change the quote
Agilex 7	High-performance	Up to 116 Gb/s, PCIe 5.0, CXL, HBM options	Quote by series and memory option, not by the word Agilex
Agilex 9	Specialized high-end/RF	Direct RF and related signal-chain parts	Rarely a second source for a standard FPGA line

Lattice FPGA Families

Lattice's portfolio is easier to understand when grouped by function rather than assuming that every family forms a simple low-to-high performance ladder.

Family	Main role	Typical design areas	RFQ note
iCE40	Very small, low-power FPGA	Portable products, simple control	Small packages; price is rarely the hard part—availability of the exact package is
MachXO/Mach-NX	Control, system management, security	Sequencing, board control, root of trust	Instant-on and I/O count matter more than LUT count
CrossLink/CrossLink-NX	Interface and video bridging	MIPI, cameras, displays	Do not substitute a generic LUT-rich part without checking hardened MIPI
Certus-NX/CertusPro-NX	General-purpose low-power FPGA	Industrial, communications, embedded	First Lattice stop when the design outgrows iCE40/MachXO
Avant-E/G/X	Mid-range FPGA	Edge processing, higher-bandwidth systems	The family that makes older Lattice comparisons obsolete

For a new design, pick the family based on the interface and power budget first. For a running product, keep the existing family unless lifecycle or allocation forces a change—the migration cost is usually larger than a unit-price gap.

Performance and Logic Resources

AMD reports system logic cells. Altera reports logic elements. Lattice families mix LUT4-style and newer fabrics. Routing, registers, RAM blocks, DSP, hard IP, and synthesis results differ. A 200K unit from two vendors is not the same device.

At portfolio scale, AMD Xilinx and Altera still reach much larger fabrics than most of the Lattice catalog. Virtex/upper Kintex and Agilex 7 are built for designs that need large fabric plus DSP, memory, and serial I/O. Lattice covers the other end with iCE40, MachXO, CrossLink, and most Nexus parts. Avant is the overlap band—not a Virtex replacement.

Before anyone compares two datasheets, lock these five items:

1. Embedded memory and the external-memory interface the board actually uses
2. DSP/multiplier count for the real signal-processing load
3. Hard IP: PCIe, Ethernet, memory controllers, MIPI, RF converters
4. Usable I/O and the package that fits the PCB
5. Timing after place-and-route—not the marketing clock number

A design with modest RTL but PCIe + DDR + SerDes often needs a higher family than a design with a large but simple control plane. Image-processing pipelines often run out of DSP before they run out of logic.

For purchasing, this means two RFQs that both say “100K FPGA” can be different commodities. Ask engineering for the family and the must-have hard IP before sending a “lowest 100K FPGA” search to every vendor.

Power, Size and High-Speed I/O

Process, clock, toggle rate, utilization, memory, I/O standard, transceiver use, junction temperature, and package all affect the number. Use the vendor power estimator on the actual RTL before freezing a family.

Typical first look:

• Tight battery, standby, or very small packages: Lattice iCE40, MachXO and Nexus-class parts. Spartan-7/Artix-7 and MAX 10/Agilex 3 are the usual AMD and Altera checks, not the other way around.
• Small board but modern interfaces: Agilex 5 E-Series already appears in packages down to 15 × 15 mm with transceivers and current memory interfaces. Artix UltraScale+ sits in a similar “not tiny, not huge” band.
• Many fast serial links, PCIe, high-rate Ethernet, HBM: Kintex/Virtex UltraScale+ and Agilex 7. Lattice Avant-G adds up to 28 × 12.5 Gb/s SerDes with PCIe Gen 3 and 10GbE-oriented configurations—useful mid-range, not the top end.

High-speed I/O also changes the rest of the BOM: more rails, more decoupling, a configuration device, sometimes a different power module set. If the board already standardizes on a Vicor or Cosel rail architecture, say so on the RFQ. The FPGA family is not the only line that moves.

Development Tools and Ecosystem

FPGA selection includes the software used to build and debug the design. The three vendors do not share a toolchain, and device support within each toolchain is family-specific.

AMD Xilinx designs use Vivado. Vitis covers software development and higher-level acceleration on the AMD platforms that support those flows. Existing Xilinx IP, timing constraints, ILA debug setups and Vivado automation stay inside that environment.

Altera designs use Quartus Prime. Newer Agilex families are tied mainly to Quartus Prime Pro. MAX, Cyclone, Arria, and Stratix devices still used on shipping boards are often still built with Quartus Prime Standard or an earlier release. Altera publishes a device-support matrix that lists which family belongs to which edition.

Lattice currently ships Radiant, Diamond, and Propel. Radiant covers Avant, MachXO5-NX, Certus-NX and CrossLink-NX. Diamond remains the tool for several older Lattice families. Propel is the processor and system-integration flow. Lattice released Radiant 2026.1 in June 2026 and publishes migration notes for designs moving from Vivado or Quartus.

Design area	What changes when the vendor changes
HDL and constraints	Timing constraints and vendor-specific primitives often have to be rewritten
IP	Memory controllers, PCIe, DSP and interface IP are not interchangeable across vendors
Verification	Timing closure and functional tests have to be run again on the new fabric
Board	Pinout, configuration scheme, package and power rails follow the new device
Project flow	Scripts, debug setup and build servers are specific to Vivado, Quartus or Radiant/Diamond

Some Lattice iCE40 designs can also be built with open-source tools such as Yosys and nextpnr. That path applies to that family; it is not the flow for Avant, Agilex or UltraScale+.

The practical effect is that two devices with similar LUT counts are still different projects if they do not share a tool chain.

Applications and Best-Fit Use Cases

None of the three vendors maps to a single industry. The same application name can land in different families once image-processing load, interface type, power and qualification are specified. The table is a first cut, not a ranking.

Application	Families usually evaluated first	Poor starting point when	What usually decides the family
Board management, sequencing, glue logic	Lattice MachXO/Mach-NX; Altera MAX 10; AMD Spartan	The part also has to carry high-speed serial or a large DSP load	Instant-on behavior, I/O count, package, temperature grade
MIPI/camera/display bridge	Lattice CrossLink/CrossLink-NX	The job is heavy ISP or DSP rather than protocol conversion	Hardened MIPI and video-oriented I/O versus general-purpose fabric
Battery and always-on edge	Lattice iCE40; then the smallest Spartan or MAX devices	The design needs fast SerDes or a large external-memory interface	Standby power and package outline
Industrial control and I/O	All three, from the low- and mid-range families above	A high-end Virtex or Agilex 7 is used only to get more I/O	Real-time I/O, industrial temperature, expected production life
Embedded vision with real DSP	AMD Artix/Kintex; Altera Agilex 5	A CrossLink part is asked to replace a processing FPGA	DSP count, memory interface, camera protocol
Telecom and networking	AMD Kintex/Virtex; Altera Agilex 5/7	The function is a small edge or bridging block	SerDes rate, channel count, Ethernet or PCIe hard IP
Data center acceleration	AMD Virtex UltraScale+; Altera Agilex 7	Lattice mid-range parts are treated as density equivalents	Fabric size, HBM or DDR bandwidth, PCIe generation
RF, radar and Direct RF	Altera Agilex 9; qualified AMD high-end families	Cost-optimized Spartan, MAX or iCE40 families	Converter integration, DSP, grade and compliance
Aerospace and defense	Qualified AMD and Altera lines	Commercial speed grades used as a proxy for qualified parts	Temperature, reliability, radiation and lifecycle requirements

 

AMD publishes XA automotive, XQ defense, and XQR space-grade variants in parts of its catalog. Those devices are specified and sold separately from commercial XC parts.

Altera’s Agilex 7 line is aimed at bandwidth-heavy networking, defense and industrial systems; Agilex 5 covers mid-range and edge designs that want newer architecture without the largest Agilex 7 configurations.

Lattice remains most visible in control, security, connectivity, and compact edge products. CrossLink, MachXO/Mach-NX, Certus, and Avant cover different slices of that space rather than one interchangeable Lattice FPGA.

Cost, Availability and Lifecycle

Cost

There is no durable rule that “Lattice is cheap, Altera is mid, Xilinx is expensive.”

Price moves with OPN, package, speed, temperature, transceivers, memory, security, qualification, volume, lifecycle status and the channel. A small Lattice part is cheap because the function is small. A larger AMD or Altera part can still win on system cost if it removes a processor, a bridge PHY or an external config device.

Published 1K ranges for mature cost-optimized devices often land roughly here—use them only as an order-of-magnitude check, then quote the exact OPN:

Band	Examples	Typical published 1K range
Very small control/IoT FPGA	Lattice iCE40, MachXO, MAX 10, low Spartan-7	about $3–$15
Mid embedded/light DSP	CrossLink-NX, Artix-7 A35-class, Cyclone 10 LP	about $10–$35
Mid with serial I/O	Artix-7 A100-class, Kintex-7, Cyclone 10 GX	about $25–$70
High-end/high-bandwidth	Kintex/Virtex UltraScale+, Agilex 7/9	hundreds to many thousands; quote only

Those bands do not include configuration memory, power modules, industrial vs commercial grade, or authorized vs independent channel premium. Send the BOM if the board has more than one programmable device; single-line web prices are not a system cost.

Availability

 

Check availability before the footprint is frozen.

Lead times are moved by family, package and grade. In recent 2026 sourcing patterns

• Mature 7 Series and many Lattice small packages are usually the easier cover.
• UltraScale+ and some Agilex lines still stretch when the package or speed grade is thin.
• Organization and brand changes on the Altera side can leave the same die documented under two names; that is a paperwork delay as much as a factory delay.

Independent distribution is used for shortage cover, last-time demand, and mismatched date-code or package needs—not as a substitute for the approved channel on a new high-volume consumer program. If the requirement is original-pack, traceable Xilinx or Altera, say that on the first email. If the requirement is to keep a 10-year industrial board alive, say that instead. The search is different.

Do not treat two OPNs as interchangeable because the family name matches. Package, speed, temperature and revision have to match the Gerber and the test program.

Lifecycle

 

Industrial, medical, communications and defense boards outlive FPGA marketing cycles.

AMD has published extended longevity for parts of the adaptive portfolio, including planned 7 Series availability through 2040 and UltraScale+ through 2045, under the manufacturer’s stated conditions. That statement applies to listed families, not to every package and not to every future purchase.

Altera’s new work is concentrated on Agilex. MAX 10, Cyclone 10, Arria 10 and Stratix 10 remain on many running BOMs; they should be quoted with an explicit production-horizon question, not assumed to follow the Agilex roadmap.

Lattice families stay in production on different clocks. Avant is the growth line; iCE40 and MachXO remain because the sockets are still there.

When a part is heading toward last-time buy, the choice is usually: last-time stock now, approve an alternate OPN, or budget a redesign. That decision needs expected remaining volume. A distributor can cover a run-out. It cannot invent a pin-compatible next-generation device that the schematic does not allow.

 

What to send with the RFQ

A usable FPGA inquiry includes:

• Complete ordering code, not only “Artix-7” or “Agilex 5”
• Quantity now and 12-month forecast
• Temperature grade and any automotive/defense/space requirement
• Whether original manufacturer packaging and full traceability are mandatory
• Whether a second-source family is allowed, and which constraints cannot move (pinout, 1.8 V banks, MIPI, PCIe generation)
• Target need-by date

Upload the BOM or send the line list. Family-level comparisons on this page are for shortlisting. The quote is always at OPN level.

Conclusion

 

There is still no single winner in Xilinx vs Altera vs Lattice.

AMD Xilinx remains the default when the design needs a wide FPGA range, mature IP, DSP and high-speed connectivity, or a later move into AMD adaptive SoCs. Altera is again an independent FPGA company, with Agilex as the current roadmap and a large installed base of MAX, Cyclone, Arria and Stratix boards to keep alive. Lattice is still the first catalog for small, low-power, control and bridging parts, and Avant is why it now belongs in some mid-range comparisons.

Pick the family against logic, DSP, memory, I/O, power, package, tools, lifecycle and supply. Then stop comparing vendors and start comparing ordering codes.

If Xilinx or Altera is already on the board file, send that OPN list. If the design is still open, include the power budget, interface list and whether the team is standardized on Vivado or Quartus. That is enough to turn this comparison into a sourcing request rather than another vendor-level essay.